The present invention relates to a semiconductor circuit for driving a clock signal line. The semiconductor circuit according to the present invention is used, for example, for a dynamic memory device.
A circuit arrangement for a prior art dynamic memory device is illustrated in FIG. 1. The dynamic memory device of FIG. 1 comprises a sense amplifier assembly 2, memory cell assemblies 11 and 12, bit lines 31 . . . 3m and 31 . . . 3m, and dynamic pull-up circuits 61 and 62, a word decoder 63, a word decoder 64, an address buffer 71, an address buffer drive signal (AD) generator 72, a word drive signal (WD) generator 73, a latch enable signal (LE) generator 74, an active pull-up signal (AP) generator 75, a word push (WP) signal generator 8, a capacitor 91 for the bootstrap operation and a grounding transistor 92. The capacitor 91 is connected between the output terminals of the word drive signal generator 73 and the word push signal generator 8.
The operation of the dynamic memory device of FIG 1 will be described below. An external address signal (Add) and a signal AD are supplied to the address buffer 71 which produces signals A0, A1, . . . , Ai and their inverted signals A0, A1, . . . , Ai which are supplied to the word decoders 63 and 64. The word decoders 63 and 64 also receive signals WD and select one of the word lines 41 through 4n and 51 through 5n. Signal LE is supplied to the transistor 92, which connects one terminal of each sense amplifier to ground, to make the corresponding sense amplifier active.
Signal AP is supplied to the dynamic pull-up circuits 61 and 62 to pull up the potential of the high side bit line to the potential V.sub.cc. The pulled up potential of the high side bit line is re-written into the memory cell selected by the word line.
The memory cell assembly 11 includes memory cells 111 through 11n, 121 through 12n, . . . , and 1nl through 1nn. The memory cell assembly 12 includes memory cells 211 through 21n, 221 through 22n, . . . , and 2nl through 2nn. The sense amplifier assembly 2 is arranged between the memory cell assemblies 11 and 12. The memory cells, which as selected by the word lines, are connected to one side of bit line pairs 31, 31; 32, 32; . . . , 3m, 3m, while the dummy cells (not shown) are connected to the other side of the above mentioned bit line pairs. When the difference is formed between the potentials of the one side and the other side of the above mentioned bit line pairs, the potential of the high side bit line is pulled up by the above described pulling up operation to the potential V.sub.cc. Such pulling up is carried out in order to cover the reduction of the potential of the high side bit line; otherwise, the potential of the high side bit line would be reduced with time due to current leakage.
Also signal WP is supplied to the WD signal line 731 through the capacitor 91 after the potential of the signal WD turns high, hence, the potential of the signal WD is pushed up to a value higher than V.sub.cc, where V.sub.cc represents the high potential.
A memory cell of the dynamic memory device of FIG. 1 comprises a series connected transistor and a capacitor (one transistor one capacitor type). Each of the memory cells is connected between a bit line and power source. The gate of each transistor is connected to a word line. Signal WD defines the potential of such word line.
When the potential of the signal WD is pushed up above the V.sub.cc value by signal WP, the potential of the word line is raised higher than the V.sub.cc value; more correctly, higher than the sum of the V.sub.cc value and the threshold voltage of the transistor of the memory cell, hence, the transistor constituting the memory cells becomes completely in an ON state, and, accordingly, the memory cells can be sufficiently charged, i.e. refreshed, by the power source of the V.sub.cc up to the potential V.sub.cc.
The word decoders 63 And 64, comprising a nor gate 642 and a transistor 641, receive address signals A0, A1, . . . , Ai and A0, A1, . . . , Ai and carry out the selection of a word line. Either the source or the drain region of the transistor 641 is connected to the WD signal generator 73, while the other is connected to a word line.
The change of the potential of the signals appearing at various portions of the device of FIG. 1 will be explained with reference to the waveforms illustrated in FIGS. 3 and 4. When the transistor 641 in the word decoder 64 turns on and the potential of the output signal of the word drive signal generator 73 becomes high, the potential W of the word line is raised as illustrated in FIG. 3. Memory cells are connected to bit lines, and potentials of the bit lines charged to the V.sub.cc value, for example, bit lines 31 and 31, are caused to become different. When such a difference in the potential is formed, the potential of the signal LE is raised, and, the transistor 92 turns ON to activate the sense amplifier 21, accordingly, the difference in the potentials of the bit lines 3m and 3m is enlarged. When a sufficient difference between the potentials B and B of the bit lines is formed, the potential of the signal AP is raised, and the potential of the high side bit line is pulled up to the V.sub.cc value. Then, after the potential of the WD signal line 731 becomes in a floating state, the signal WP is raised, the potential of the word line is pushed up above the V.sub.cc value, and the transistor 121 of the memory cell is made to be completely in an ON state as illustrated in FIG. 4.
The structure of the output side portion of the word drive signal generator 73 is as illustrated in FIG. 1. When the transistor 732 is turned ON and the transistor 733 is turned OFF by the signals S1 and S2, the potential of the WD signal line 731 is raised to the V.sub.cc value, as illustrated in FIG. 4. While the potential of the signal WP is low, the capacitor 91 is connected between the WD signal line 731 and ground and acts as a load for the output transistors 732 and 733.
However, in order to satisfactorily push up the potential of the word line, the capacitor 91 is required to have a large capacitance, which is the same as or larger than the stray capacitance, the value of which is, for example, 10 to 20 pF for the WD signal line 731 and word lines, which makes the capacitor load a large one. If such a large capacitor load is used, the rising speed of the potential of the signal WD becomes inevitably slow, the access time of the memory device is increased, and the operational characteristic of the memory device deteriorates.